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  ht48r05a-1/ht48c05/ ht48r06a-1/ht48c06/ht48r08a-1 cost-effective i/o type 8-bit mcu selection table part no. vdd program memory data memory i/o timer int. pfd stack package types ht48r05a-1 ht48c05 2.2v~5.5v 0.5k  14 32  8 13 8-bit  1 2  2 16ssop/nsop, 18dip/sop ht48r06a-1 ht48c06 2.2v~5.5v 1k  14 64  8 13 8-bit  1 2  2 16ssop/nsop, 18dip/sop ht48r08a-1 2.2v~5.5v 2k  14 96  8 13 8-bit  1 2  2 16ssop/nsop, 18dip/sop rev. 1.51 1 december 30, 2008 general description the ht48r05a-1/ht48c05, ht48r06a-1/ht48c06 and ht48r08a-1 are 8-bit high performance, risc ar - chitecture microcontroller devices specifically designed for cost-effective multiple i/o control product applica - tions. the mask version ht48c05 and ht48c06 are fully pin and functionally compatible with the otp ver - sion ht48r05a-1 and ht48r06a-1 devices. the advantages of low power consumption, i/o flexibil - ity, timer functions, oscillator options, halt and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem con - trollers, etc. features  operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v  13 bidirectional i/o lines  an interrupt input shared with an i/o line  8-bit programmable timer/event counter with over - flow interrupt and 8-stage prescaler  on-chip crystal and rc oscillator  watchdog timer  program memory rom: 512  14 for ht48r05a-1/ht48c05 1024  14 for ht48r06a-1/ht48c06 2048  14 for ht48r08a-1  data memory ram 32  8 for ht48r05a-1/ht48c05 64  8 for ht48r06a-1/ht48c06 96  8 for ht48r08a-1  buzzer driving pair and pfd supported  halt function and wake-up feature reduce power consumption  up to 0.5  s instruction cycle with 8mhz system clock at v dd =5v  allinstructionsinoneortwomachinecycles  14-bit table read instruction  two-level subroutine nesting  bit manipulation instruction  powerful instructions: 62 for ht48r05a-1/ht48c05 63 for ht48r06a-1/ht48c06 and ht48r08a-1  low voltage reset function  16-pin ssop/nsop package 18-pin dip/sop package technical document  tools information  faqs  application note  ha0003e communicating between the ht48 & ht46 series mcus and the ht93lc46 eeprom  ha0013e ht48 & ht46 lcm interface design  ha0016e writing and reading to the ht24 eeprom with the ht48 mcu series  ha0018e controlling the ht1621 lcd controller with the ht48 mcu series  ha0049e read and write control of the ht1380  ha0075e mcu reset and oscillator circuits application note
block diagram pin assignment ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 2 december 30, 2008         
                                                                  
              !        !   " # $ %   # $ %   " & $  '  ( " ' $    )     )          % !   *  # + $  " ( $ '  # %  ' + $ %      # + $  " ( $ '  #  % (  , %       -  . '  $ %   ' ! ' #  / % # %  $                % + ( 0 %                   % + ( 0 %              1   2     
            3  
      
                   4  2 1  3

3  1 2  4 5 2 1  3
 5
3  1 2  4      1   2     
       3  
                               
            
            
  
                  
            
            
  
         
pin description pin name i/o options description pa0~pa7 i/o pull-high* wake-up bidirectional 8-bit input/output port. each bit can be configured as wake-up input by options. software instructions determine the cmos output or schmitt trigger input with a pull-high resistor (determined by pull-high op - tions). pb0/bz pb1/bz pb2 i/o pull-high* i/o or bz/bz bidirectional 3-bit input/output port. software instructions determine the cmos output or schmitt trigger input with a pull-high resistor (determined by pull-high options). the pb0 and pb1 are pin-shared with the bz and bz , respectively. once the pb0 and pb1 are selected as buzzer driving outputs, the output signals come from an internal pfd generator (shared with a timer/event counter). vss  negative power supply, ground pc0/int pc1/tmr i/o pull-high* bidirectional i/o lines. software instructions determine the cmos output or schmitt trigger input with a pull-high resistor (determined by pull-high op - tions). the external interrupt and timer input are pin-shared with the pc0 and pc1, respectively. the external interrupt input is activated on a high to low transition. res i  schmitt trigger reset input. active low vdd  positive power supply osc1 osc2 i o crystal or rc osc1, osc2 are connected to an rc network or crystal (determined by op - tions) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. * all pull-high resistors are controlled by an option bit. absolute maximum ratings supply voltage ...........................v ss  0.3v to v ss +6.0v storage temperature ............................  50  cto125  c input voltage..............................v ss  0.3v to v dd +0.3v operating temperature...........................  40  cto85  c i ol total ..............................................................150ma i oh total............................................................  100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under  absolute maximum ratings  may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage  f sys =4mhz 2.2  5.5 v  f sys =8mhz 3.3  5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz  0.6 1.5 ma 5v  24ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz  0.8 1.5 ma 5v  2.5 4 ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz  48ma ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 3 december 30, 2008
symbol parameter test conditions min. typ. max. unit v dd conditions i stb1 standby current (wdt enabled) 3v no load, system halt  5  a 5v  10  a i stb2 standby current (wdt disabled) 3v no load, system halt  1  a 5v  2 v il1 input low voltage for i/o ports, tmr and int  0  0.3v dd v v ih1 input high voltage for i/o ports, tmr and int  0.7v dd  v dd v v il2 input low voltage (res )  0  0.4v dd v v ih2 input high voltage (res )  0.9v dd  v dd v v lvr low voltage reset  lvr enabled 2.7 3.0 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48  ma 5v 10 20  i oh i/o port source current 3v v oh =0.9v dd  2  4  ma 5v  5  10  r ph pull-high resistance 3v  20 60 100 k 5v 10 30 50 a.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc, rc osc)  2.2v~5.5v 400  4000 khz  3.3v~5.5v 400  8000 khz f timer timer i/p frequency (tmr)  2.2v~5.5v 0  4000 khz  3.3v~5.5v 0  8000 khz t wdtosc watchdog oscillator period 3v  45 90 180  s 5v 32 65 130 t wdt1 watchdog time-out period (rc) 3v without wdt prescaler 11 23 46 ms 5v 8 17 33 t wdt2 watchdog time-out period (system clock)  without wdt prescaler  1024  t sys t res external reset low pulse width  1  s t sst system start-up timer period  wake-up from halt  1024  t sys t int interrupt pulse width  1  s t lvr low voltage width to reset  0.25 1 2 ms note: t sys =1/f sys ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 4 december 30, 2008
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 5 december 30, 2008 functional description execution flow the system clock for the microcontroller is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter  pc the program counter (pc) controls the sequence in which the instructions stored in program rom are exe - cuted and its contents specify full range of program memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required.  
 3    
 3    
 3   6 % $ ( .      7   8 9 % ( " $ %      7   : 8 6 % $ ( .      7   ; 8 9 % ( " $ %      7   8 6 % $ ( .      7   ;
8 9 % ( " $ %      7   ; 8     ;   ;
* + $ % !   0  ( <  
 7    # 0 * 8   execution flow mode program counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000 external interrupt 00000000100 timer/event counter overflow 00000001000 skip program counter+2 loading pcl *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *10~*0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits for ht48r05a-1/ht48c05, the program counter is 9 bits wide, i.e. from *8~*0 for ht48r06a-1/ht48c06, the program counter is 10 bits wide, i.e. from *9~*0 for ht48r08a-1, the program counter is 11 bits wide, i.e. from *10~*0
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 6 december 30, 2008 program memory  rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 512  14 bits (ht48r05a-1/ht48c05), 1024  14 bits (ht48r06a-1/ht48c06) or 2048  14 bits (ht48r08a-1), addressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage:  location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h.  location 004h this area is reserved for the external interrupt service program. if the int input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h.  location 008h this area is reserved for the timer/event counter inter - rupt service program. if a timer interrupt results from a timer/event counter overflow, and if the interrupt is en - abled and the stack is not full, the program begins ex - ecution at location 008h.  table location any location in the program memory can be used as look-up tables. the instructions  tabrdc [m]  (the current page, 1 page=256 words) and  tabrdl [m]  (the last page; however this statement is not valid for the ht48r05a-1/ht48c05 devices) transfer the con - tents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the ta - ble is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the re - maining 2 bits are read as  0  . the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), which indicates the table location. before accessing the table, the lo - cation must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read in - struction used in the isr. errors can occur. in other words, using the table read instruction in the main rou - tine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read in - struction. it will not be enabled until the tblh has 6 6 =
  = 3 6 6 =  # ' $ ' 0 ' > $ '  #   % ( $    ' ! %     " # $ %   # $ %   " & $   % ( $    ' ! %     " # $ %   # $ %   " & $   % ( $    # ' $ ' 0 ' > $ '  #   % ( $     4 =        
         =    =       
     9 $ %  # 0   # $ %   " & $   % ( $    ' ! %     " # $ %   # $ %   " & $   % ( $    # ' $ ' 0 ' > $ '  #   % ( $          
   =  6 6 =   ? ' $ +   ? ' $ +   $   ! & 0 % ! % # $ % ,   ? ' $ + 9 $ %  # 0   # $ %   " & $   % ( $   9 $ %  # 0   # $ %   " & $   % ( $   program memory instruction table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: table location bits p10~p8: current program counter bits @7~@0: table pointer bits for ht48r05a-1/ht48c05, the table address location is 9 bits, i.e. from *8~*0 for ht48r06a-1/ht48c06, the table address location is 10 bits, i.e. from *9~*0 for ht48r08a-1, the table address location is 11 bits, i.e. from *10~*0
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 7 december 30, 2008 been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register  stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is or - ganized into 2 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledgment, the con - tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program coun - ter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a  call  is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 2 return ad- dresses are stored). data memory  ram the data memory is designed with 49  8 bits (ht48r05a-1/ht48c05), 81  8 bits (ht48r06a-1/ ht48c06) or 113  8 bits (ht48r08a-1). the data memory is divided into two functional groups: special function registers and general purpose data memory 32  8 (ht48r05a-1/ht48c05), 64  8 (ht48r06a-1/ ht48c06) or 96  8 (ht48r08a-1). most are read/write, but some are read only. the special function registers include the indirect ad - dressing register (00h), timer/event counter (tmr;0dh), timer/event counter control register (tmrc;0eh), program counter lower-order byte regis - ter (pcl;06h), memory pointer register (mp;01h), ac - cumulator (acc;05h), table pointer (tblp;07h), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control register (intc;0bh), watchdog timer option setting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h) and i/o control registers (pac;13h, pbc;15h, pcc;17h). the remain - ing space before the 60h (ht48r05a-1/ht48c05), 40h (ht48r06a-1/ht48c06) or 20h (ht48r08a-1) is reserved for future expanded usage and reading these locations will get  00h  . the general purpose data memory, addressed from 60h to 7fh (ht48r05a-1/ ht48c05), 40h to 7fh (ht48r06a-1/ht48c06) or 20h to 7fh (ht48r08a-1), is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by  set [m].i  and  clr [m].i  . they are also indirectly accessible through memory pointer register (mp;01h). indirect addressing register location 00h is an indirect addressing register that is not physically implemented. any read/write operation of [00h] accesses data memory pointed to by mp (01h). reading location 00h itself indirectly will return the re - sult 00h. writing indirectly results in no operation. the memory pointer register mp (01h) is a 7-bit register. the bit 7 of mp is undefined and reading will return the result  1  . any writing operation to mp will only transfer the lower 7-bit data to mp. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit  alu this circuit performs 8-bit arithmetic and logic opera- tions. the alu provides the following functions:  arithmetic operations (add, adc, sub, sbc, daa)  logic operations (and, or, xor, cpl)  rotation (rl, rr, rlc, rrc)  increment and decrement (inc, dec)  branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register  status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition opera - tions related to the status register may give different re - sults from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the  clr wdt  or  halt  instruction. the pdf flag can be affected only by executing the  halt  or  clr wdt  instruction or a system power-up.
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 8 december 30, 2008 the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control reg - ister (intc;0bh) contains the interrupt control bits to set the enable or disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flag is recorded. if a certain in - terrupt requires servicing within the service routine, the emi bit and the corresponding bit of intc may be set to allow interrupt nesting. if the stack is full, the interrupt re - quest will not be acknowledged, even if the related inter - rupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre - vented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by & % ( ' 0   "  &  + %  $   % !   *   =  = 
=  3 =   =  1 =  2 =   =  4 =  5 =   =   =   =   =  =  6 =  = =
= 3 =  = 1 = 2 =  =  # , '  % ( $   , ,  % + + ' #   %  ' + $ %         -   -    - =                                @   # " + % , a  % ,  +  b   b / % # %  0   "  &  + %  $   % !   * 7 5 2   * $ % + 8  6 = 6 =
 = 4 =        
  =  = 
=  3 =   =  1 =  2 =   =  4 =  5 =   =   =   =   =  =  6 =  = =
= 3 =  = 1 = 2 =  =  # , '  % ( $   , ,  % + + ' #   %  ' + $ %         -   -    - =                                / % # %  0   "  &  + %  $   % !   * 7 2    * $ % + 8  6 = 3 6 =   = 4 =       
     & % ( ' 0   "  &  + %  $   % !   *   =  = 
=  3 =   =  1 =  2 =   =  4 =  5 =   =   =   =   =  =  6 =  = =
= 3 =  = 1 = 2 =  =  # , '  % ( $   , ,  % + + ' #   %  ' + $ %         -   -    - =                                / % # %  0   "  &  + %  $   % !   * 7 3
  * $ % + 8  6 = 1 6 = 2  = 4 =        
      & % ( ' 0   "  &  + %  $   % !   * ram mapping bit no. label function 0 c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1 ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3 ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the  clr wdt  instruction. pdf is set by executing the  halt  instruction. 5 to to is cleared by system power-up or executing the  clr wdt  or  halt  instruction. to is set by a wdt time-out. 6~7  unused bit, read as  0  status (0ah) register
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 9 december 30, 2008 pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. external interrupts are triggered by a high to low transi - tion of int and the related interrupt request flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the interrupt re - quest flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf; bit 5 of intc), caused by a timer overflow. when the interrupt is enabled, the stack is not full and the tf bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (tf) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the  reti  instruction is executed or the emi bit and the related in - terrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine,  ret  or  reti  may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. no. interrupt source priority vector a external interrupt 1 04h b timer/event counter overflow 2 08h the timer/event counter interrupt request flag (tf), ex - ternal interrupt request flag (eif), enable timer/event counter bit (eti), enable external interrupt bit (eei) and enable master interrupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eei, eti are used to control the en - abling/disabling of interrupts. these bits prevent the re - quested interrupt from being serviced. once the interrupt request flags (tf, eif) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the  call subroutine  within the interrupt subroutine. in - terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam - aged once the  call  operates in the interrupt subrou - tine. oscillator configuration there are two oscillator circuits in the microcontroller. both are designed for system clocks, namely the rc os - cillator and the crystal oscillator, which are determined by the options. no matter what oscillator type is se - lected, the signal provides the system clock. the halt mode stops the system oscillator and ignores an exter - nal signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vdd is required and the resistance must range from 24k to 1m . the system clock, divided by 4, is available on osc2, which can be used to synchro - nize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of oscil - lation may vary with vdd, temperatures and the chip it - self due to process variations. it is, therefore, not suitable for timing sensitive operations where an accu - rate oscillator frequency is desired. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 eti controls the timer/event counter interrupt (1= enabled; 0= disabled) 3, 6~7  unused bit, read as  0  4 eif external interrupt request flag (1= active; 0= inactive) 5 tf internal timer/event counter request flag (1= active; 0= inactive) intc (0bh) register   * + $ 0   + ( ' 0 0 $      + ( ' 0 0 $      
     & % #    ' #  
       & 6      system oscillator
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 10 december 30, 2008 if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. instead of a crystal, a resona - tor can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required (if the oscillating fre - quency is less than 1mhz). the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 65  s at 5v. the wdt oscillator can be disabled by options to conserve power. watchdog timer  wdt the clock source of wdt is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4), decided by options. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by an op - tion. if the watchdog timer is disabled, all the execu - tions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 65  s at 5v normally) is selected, it is first di- vided by 256 (8-stage) to get the nominal time-out pe- riod of approximately 17ms at 5v. this time-out period may vary with temperatures, vdd and process varia- tions. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1 and ws0 are all equal to  1  , the division ratio is up to 1:128, and the maximum time-out period is 2.1s at 5v seconds. if the wdt oscillator is dis - abled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its pro - tecting purpose. in this situation the logic can only be re - started by external logic. the high nibble and bit 3 of the wdts are reserved for user
s defined flags, which can be used to indicate some specified status. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register the wdt overflow under normal operation will initialize  chip reset  and set the status bit  to  . but in the halt mode, the overflow will initialize a  warm reset  , and only the program counter and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res), software instruction and a  halt  in - struction. the software instruction include  clr wdt  and the other set  clr wdt1  and  clr wdt2  .of these two types of instruction, only one can be active de - pending on the option  clr wdt times selection op - tion  .ifthe  clr wdt  is selected (i.e. clrwdt times equal one), any execution of the  clr wdt  instruction will clear the wdt. in the case that  clr wdt1  and  clr wdt2  are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. power down operation  halt the halt mode is initialized by the  halt  instruction and results in the following...  the system oscillator will be turned off but the wdt oscillator keeps running (if the wdt oscillator is se - lected).  the contents of the on chip ram and registers remain unchanged.  wdt and wdt prescaler will be cleared and re - counted again (if the wdt clock is from the wdt os - cillator).  all of the i/o ports maintain their original status.  the pdf flag is set and the to flag is cleared. * + $ % !   0  ( <   4 : ? ' $    " # $ %        % + ( 0 %   : ? ' $    " # $ %  4 : $  :          ' ! % :  " $    
 & $ '  # % 0 % ( $      watchdog timer
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 11 december 30, 2008 the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a  warm reset  . after the to and pdf flags are examined, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or execut - ing the  clr wdt  instruction and is set when execut - ing the  halt  instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; the others keep their orig - inal status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by the options. awakening from an i/o port stim - ulus, the program will resume execution of the next in - struction. if it is awakening from an interrupt, two sequences may happen. if the related interrupt is dis - abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regu - lar interrupt response takes place. if an interrupt request flag is set to  1  before entering the halt mode, the wake-up function of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (sys- tem clock period) to resume normal operation. in other words, a dummy period will be inserted after wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur:  res reset during normal operation  res reset during halt  wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a  warm re - set  that resets only the program counter and sp, leav - ing the other circuits in their original state. some regis - ters remain unchanged during other reset conditions. most registers are reset to the  initial condition  when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different  chip resets  . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note:  u  stands for  unchanged  to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able the sst delay.      <   <   c   6      <   c  6  c  6                                   reset circuit note: most applications can use the basic reset cir - cuit as shown, however for applications with ex - tensive noise, it is recommended to use the hi-noise reset circuit.   !  % + % $    =  -    0 , % + % $ * + $ % !  % + % $   : ? ' $  ' & & 0 %   " # $ %    reset configuration $        ' ! % :  " $  . ' &   % + % $ reset timing chart
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 12 december 30, 2008 an extra option load time delay is added during system reset (power-up, wdt time-out at normal mode or res reset). the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack the states of the registers is summarized in the table. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* program counter 000h 000h 000h 000h 000h mp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu tmr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu pbc ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu pc ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu pcc ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu note:  *  means  warm reset   u  means  unchanged   x  means  unknown  timer/event counter a timer/event counter (tmr) is implemented in the microcontroller. the timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock. using external clock input allows the user to count exter - nal events, measure time internals or pulse widths, or generate an accurate time base. while using the inter - nal clock allows the user to generate an accurate time base. the timer/event counter can generate pfd signal by us - ing external or internal clock and pfd frequency is de - termine by the equation f int /[2  (256-n)]. there are 2 registers related to the timer/event counter; tmr ([0dh]), tmrc ([0eh]). two physical registers are mapped to tmr location; writing tmr makes the start - ing value be placed in the timer/event counter preload register and reading tmr retrieves the contents of the timer/event counter. the tmrc is a timer/event counter control register, which defines some options.
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 13 december 30, 2008 the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr). the counting is based on the f int clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffh. once over - flow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt re - quest flag (tf; bit 5 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr has received a transient from low to high (or high to low if the te bits is  0  ) it will start counting until the tmr returns to the orig - inal level and resets the ton. the measured result will remain in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it re - ceives further transient pulse. note that, in this operat - ing mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will be cleared au - tomatically after the measurement cycle is completed. but in the other two modes the ton can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources. no matter what the opera - tion mode is, writin ga0toetican disable the interrupt service. bit no. label function 0~2 psc0~psc2 to define the prescaler stages, psc2, psc1, psc0= 000: f int =f sys /2 001: f int =f sys /4 010: f int =f sys /8 011: f int =f sys /16 100: f int =f sys /32 101: f int =f sys /64 110: f int =f sys /128 111: f int =f sys /256 3te to define the tmr active edge of the timer/event counter (0=active on low to high; 1=active on high to low) 4 ton to enable or disable timer counting (0=disabled; 1=enabled) 5  unused bit, read as  0  6 7 tm0 tm1 to define the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc (0eh) register                  " 0 + %   ' , $ .  % + "  % ! % # $   , %    # $   0  ' ! %   d % # $    " # $ %    % 0  ,  %  ' + $ %   ' ! %   d % # $   " # $ %   $   " + % 0  ,  d %   0  e $    # $ %   " & $ 
    4 : + $  %    % + ( 0 %  4 :            
    timer/event counter
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 14 december 30, 2008                
               7    a      # 0 * 8                   # 0 *              # 0 * * + $ % !   < % : " & 7     # 0 * 8 % ,   $  %  ' + $ %       7    a      # 0 * 8   # $   0   ' $  " 0 0 : . '  .  $   " +   ' $ %    # $   0  %  ' + $ %   . ' &  % + % $ % ,    # $   0  %  ' + $ %    ' $ %   $  %  ' + $ %   $   ' $  f  ) f  f  ) f input/output ports in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmr) is read, the clock will be blocked to avoid errors. as clock blocking may results in a counting error, this must be taken into consideration by the programmer. the bit0~2 of the tmrc can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. the definitions are as shown. the overflow signal of the timer/event counter can be used to generate pfd signals for buzzer driving. input/output ports there are 13 bidirectional input/output lines in the microcontroller, labeled from pa to pc, which are mapped to the data memory of [12h], [14h] and [16h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction  mov a,[m]  (m=12h, 14h or 16h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be re- configured dynamically (i.e. on-the-fly) under software control. to function as an input, the corresponding latch of the control register must write  1  . the input source also depends on the control register. if the control regis - ter bit is  1  , the input will read the pad state. if the con - trol register bit is  0  , the contents of the latches will move to the internal bus. the latter is possible in the  read-modify-write  instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h and 17h. after a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). each bit of these input/output latches can be set or cleared by  set [m].i  and  clr [m].i  (m=12h, 14h or 16h) instructions. some instructions first input data and then follow the output operations. for example,  set [m].i  ,  clr [m].i  ,  cpl [m]  ,  cpla [m]  read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. the highest 6-bit of port c and 5 bits of port b are not physically implemented; on reading them a  0  is returned whereas writing then results in a no-operation. see application note. there is a pull-high option available for all i/o lines. once the pull-high option is selected, all i/o lines have pull-high resistors. otherwise, the pull-high resistors are absent. it should be noted that a non-pull-high i/o line operating in input mode will cause a floating state. the pb0 and pb1 are pin-shared with bz and bz signal, respectively. if the bz/bz option is selected, the output
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 15 december 30, 2008 signal in output mode of pb0/pb1 will be the pfd signal generated by timer/event counter overflow signal. the input mode always remaining its original functions. once the bz/bz option is selected, the buzzer output signals are controlled by pb0 data register only. the i/o functions of pb0/pb1 are shown below. pb0 i/o i i i i o o o o o o pb1 i/o i o o o i i i o o o pb0/pb1 mode x c b b c b b c b b pb0 data x x 0 1 d 0 1 d 0 01 pb1 data x d x x x x x d 1 xx pb0 pad status i i i i d 0 b d 0 0b pb1 pad status i d 0 b i i i d 1 0b note: i: input; o: output; d, d 0 ,d 1 : data; b: buzzer option, bz or bz ; x: don't care c: cmos output the pc0 and pc1 are pin-shared with int , tmr and pins respectively. it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. low voltage reset  lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications:  the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function.  the lvr uses the  or  function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera - tion at 4mhz system clock. 1 c 1  3 c  
c
  c 5         -  1 c 1     1 c 1   -   c 5    % + % $  '  # 0 % + % $ g g
   ! 0   & %  $ '  # % + % $ -    % $ % ( $    0 $  % low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode.
application circuits note: 1. crystal/resonator system oscillators for crystal oscillators, c1 and c2 are only required for some crystal frequencies to ensure oscillation. for resonator applications c1 and c2 are normally required for oscillation to occur. for most applications it is not necessary to add r1. however if the lvr function is disabled, and if it is required to stop the oscillator when vdd falls below its operating range, it is recommended that r1 is added. the values of c1 and c2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. reset circuit the reset circuit resistance and capacitance values should be chosen to ensure that vdd is stable and re - mains within its operating voltage range before the res pin reaches a high level. ensure that the length of the wiring connected to the res pin is kept as short as possible, to avoid noise interference. 3. for applications where noise may interfere with the reset circuit and for details on the oscillator external com - ponents, refer to application note ha0075e for more information. ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 16 december 30, 2008 options the following table shows all kinds of options in the microcontroller. all of the options must be defined to ensure proper system functioning. items options 1 wdt clock source: wdtosc or f sys /4 2 wdt function: enable or disable 3 lvr function: enable or disable 4 clrwdt instruction(s): one or two clear wdt instruction(s) 5 system oscillator: rc or crystal 6 pull-high resistors (pa~pc): none or pull-high 7 bz function: enable or disable 8 pa0~pa7 wake-up: enable or disable                                
       
            
            
   
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ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 17 december 30, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5  s and branch or call instructions would be im - plemented within 1  s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be  clr pcl  or  mov pcl, a  . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 18 december 30, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the  set [m].i  or  clr [m].i  instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the  halt  in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 19 december 30, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the  clr wdt1  and  clr wdt2  instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both  clr wdt1  and  clr wdt2  instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc  and  [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc  and  x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc  and  [m] affected flag(s) z ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 20 december 30, 2008
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 21 december 30, 2008
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1
s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1
s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m]  1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m]  1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 22 december 30, 2008
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc  or  [m] affected flag(s) z ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 23 december 30, 2008
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc  or  x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc  or  [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). if an in- terrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 24 december 30, 2008
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 25 december 30, 2008
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc  [m]  c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc  [m]  c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]  1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m]  1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 26 december 30, 2008
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc  [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc  [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc  x affected flag(s) ov, z, ac, c ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 27 december 30, 2008
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 28 december 30, 2008
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc  xor  [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc  xor  [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc  xor  x affected flag(s) z ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 29 december 30, 2008
package information 16-pin ssop (150mil) outline dimensions symbol dimensions in mil min. nom. max. a 228  244 b 150  157 c8  12 c
189  197 d54  60 e  25  f4  10 g22  28 h7  10  0  8  ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 30 december 30, 2008 2 5 4     6  i / = 
16-pin nsop (150mil) outline dimensions  ms-012 symbol dimensions in mil min. nom. max. a 228  244 b 150  157 c12  20 c
386  394 d  69 e  50  f4  10 g16  50 h7  10  0  8  ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 31 december 30, 2008 2 5 4      6 / =  i
18-pin dip (300mil) outline dimensions  ms-001d (see fig1) symbol dimensions in mil min. nom. max. a 880  920 b 240  280 c 115  195 d 115  150 e14  22 f45  70 g  100  h 300  325 i  430  ms-001d (see fig1) symbol dimensions in mil min. nom. max. a 845  880 b 240  280 c 115  195 d 115  150 e14  22 f45  70 g  100  h 300  325 i  430 ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 32 december 30, 2008 4  5     6 / =  fig1. full lead packages 4  5     6 / =  fig2. 1 / 2 lead packages
 mo-095a (see fig2) symbol dimensions in mil min. nom. max. a 845  885 b 275  295 c 120  150 d 110  150 e14  22 f45  60 g  100  h 300  325 i  430 ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 33 december 30, 2008
18-pin sop (300mil) outline dimensions  ms-013 symbol dimensions in mil min. nom. max. a 393  419 b 256  300 c12  20 c
447  463 d  104 e  50  f4  12 g16  50 h8  13  0  8  ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 34 december 30, 2008 4  5     6 / =   i
product tape and reel specifications reel dimensions ssop 16s symbol description dimensions in mm a reel outer diameter 330.0  1.0 b reel inner diameter 100.0  1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0  0.5 t1 space between flange 12.8 +0.3/-0.2 t2 reel thickness 18.2  0.2 sop 16n (150mil) symbol description dimensions in mm a reel outer diameter 330.0  1.0 b reel inner diameter 100.0  1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0  0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2  0.2 ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 35 december 30, 2008     

sop 18w symbol description dimensions in mm a reel outer diameter 330.0  1.0 b reel inner diameter 100.0  1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0  0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2  0.2 ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 36 december 30, 2008
carrier tape dimensions ssop 16s symbol description dimensions in mm w carrier tape width 12.0 +0.3/-0.1 p cavity pitch 8.0  0.1 e perforation position 1.75  0.10 f cavity to perforation (width direction) 5.5  0.1 d perforation diameter 1.55  0.10 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0  0.1 p1 cavity to perforation (length direction) 2.0  0.1 a0 cavity length 6.4  0.1 b0 cavity width 5.2  0.1 k0 cavity depth 2.1  0.1 t carrier tape thickness 0.30  0.05 c cover tape width 9.3  0.1 ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 37 december 30, 2008        6 $ )          & ( <  %  & ' #   # ,  $ . %   % % 0  .  0 % +  %  0  ( $ % ,   #  $ . %  + ! %  + ' , % c % % 0  =  0 %
sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.0  0.3 p cavity pitch 8.0  0.1 e perforation position 1.75  0.1 f cavity to perforation (width direction) 7.5  0.1 d perforation diameter 1.55 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.0 p0 perforation pitch 4.0  0.1 p1 cavity to perforation (length direction) 2.0  0.1 a0 cavity length 6.5  0.1 b0 cavity width 10.3  0.1 k0 cavity depth 2.1  0.1 t carrier tape thickness 0.30  0.05 c cover tape width 13.3  0.1 sop 18w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 16.0  0.1 e perforation position 1.75  0.1 f cavity to perforation (width direction) 11.5  0.1 d perforation diameter 1.5  0.1 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0  0.1 p1 cavity to perforation (length direction) 2.0  0.1 a0 cavity length 10.9  0.1 b0 cavity width 12.0  0.1 k0 cavity depth 2.8  0.1 t carrier tape thickness 0.30  0.05 c cover tape width 21.3  0.1 ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 38 december 30, 2008
ht48r05a-1/ht48c05/ht48r06a-1/ht48c06/ht48r08a-1 rev. 1.51 39 december 30, 2008 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright  2007 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek
s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.


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